1. Field of the Invention
The invention relates to a data processing arrangement comprising a control unit and a memory device connected therewith. The memory unit contains a memory provided with a first and a second field, so that for each memory word in the first field at least one error protection bit can be stored at a corresponding address in the second field. The memory device contains an error protection bit generator connected to the first field for the generating, on the basis of a memory word presented, at least one error protection bit. The memory device is also provided with an error protection device for carrying out, together with the error protection bit generator and the second field, an error protection operation on a memory word presented. The control unit contains an error protection instruction generator for the generation of an error protection instruction. The error protection device contains a coincidence circuit, a first input of which is connected to an output of the error protection bit generator and a second input of which is connected to a data output of the second field. The error protection device is provided in order to deliver the result of an error protection operation to a result output under the control of an error protection instruction, received at a control input and on reading a memory word.
2. Background of the Invention
A data processing arrangement of this type is known from the German patent application No. 34 04 782. In the known data processing arrangement, the error protection bit generator is formed by a parity bit generator which generates a parity bit for each memory word presented. When writing the memory word in the first field, the known arrangement writes this parity bit in the second field at an address that corresponds to the address at which the relevant memory word is written in the first field. The recognition of parity errors when reading memory words operates further in the known manner. However, in order to use the known data processing arrangement to investigate for analytical purposes whether memory words are read at particular addresses in memory, the parity bit at these addresses in the second field is first deliberately set wrong.
If a read operation is carried out at one of these addresses a wrong parity bit is then delivered to the coincidence circuit, with the result that the error protection operation has a negative result. The control unit is then notified of that negative result and is thus informed of the fact that a read operation has taken place at that particular address. In this way, the control unit can take the necessary measures.
A disadvantage of the known arrangement, however, is that it is only in read operations that it is possible to investigate whether these addresses, at which the error protection bit has been set wrong, are addressed. The known arrangement cannot therefore be used, for example, to investigate whether data is being written at these addresses. In addition, since a wrong parity bit is used, the arrangement is completely dependent on the content of the memory location in the first field at which it is desired to investigate access operations.